1. Technical Field
Various embodiments relate to a semiconductor integrated circuit, and more particularly, to a control circuit for a bit-line sense amplifier (BLSA), a semiconductor memory apparatus having the same, and an operating method thereof.
2. Related Art
A semiconductor memory apparatus, or particularly, DRAM uses a bit-line sense amplifier to sufficiently amplify charge stored in a memory cell, when reading information of the memory cell.
Referring to FIG. 1, the control circuit 10 for a bit-line sense amplifier may include a bank active signal generator 101, a sense amplifier enable signal generator 103, a control signal generator 105, and a sense amplifier driver 107.
The bank active signal generator 101 may be configured to generate a bank enable signal BAb for driving a specific bank in response to an active command ACT and a precharge command PCG.
The sense amplifier enable signal generator 103 may be configured to delay the bank enable signal BAb by a preset time and generate a sense amplifier enable signal SAEN.
The control signal generator 105 may be configured to generate sense amplifier driving control signals SAP and SAN in response to the sense amplifier enable signal SAEN.
The sense amplifier driver 107 may be configured to generate sense amplifier power signal RTO and SB in response to the sense amplifier driving control signals SAP and SAN.
Referring to FIG. 2, as an active command ACT synchronized with a clock signal CLK is provided, the bank active signal BAb is activated. Then, a word line enable signal WLEN is activated to apply a preset voltage to a word line. When the word line enable signal WLEN is activated, data stored in a memory cell coupled to the enabled word line is transmitted to a bit line pair BL and BLb, and charge sharing occurs between the bit line pair BL and BLb.
Then, the bit-line sense amplifier amplifies and senses the charge stored in the bit line pair BL and BLb in response to the sense amplifier power signals RTO and SB generated from the control circuit 10 for a bit-line sense amplifier.
Then, as the read command RD is applied, the data sensed through the bit-line sense amplifier is transmitted through a local input/output line.
The time tRCD (RAS to CAS delay) required until the read command RD is provided after the active command ACT is closely related to the time required until a voltage difference between the bit line pair BL and BLb approaches a preset level ΔV after charge sharing is started between the bit line pair BL and BLb by the word line enable signal WLEN, that is, a charge sharing time.
FIGS. 3 and 4 are diagrams for explaining a charge sharing time depending on a read environment.
FIG. 3 illustrates the voltage change of the bit line pair BL and BLb when the bit-line sense amplifier operates at high speed according to PVT (Process Voltage Temperature) variation, and FIG. 4 illustrates the voltage change of the bit line pair BL and BLb when the BLSA operates at low speed.
In the environment where the bit-line sense amplifier operates at high speed, a charge sharing time t1 required until the voltage difference between the bit line pair BL and BLb approaches the preset level ΔV is shorter than a charge sharing time t2 in the environment where the BLSA operates at low speed.
Thus, the time tRCD must be set in such a condition that the operating speed is optimized while the voltage difference between the bit line pair BL and BLb approaches the preset level ΔV.
When the time tRCD is lengthened, the charge sharing time may be increased to secure a sufficient voltage difference ΔV between the bit line pair BL and BLb; but a sensing start time may be delayed. Also, when the time tRCD is shortened, the charge sharing time may be reduced, and charge sharing may not be sufficiently performed. Then, a fail may occur in the bit line sense amplifier.
The charge sharing time may be set to such a level that the voltage difference ΔV between the bit line pair BL and BLb is saturated. In general, the time tRCD may be set on the basis of the charge sharing time under the worst PVT condition that lengthens the charge sharing time, for example, a PVT condition of a low-speed operation transistor, skew, temperature, or low voltage.
That is, in a current semiconductor memory apparatus, the time tRCD is fixed according to the worst PVT condition. However, the fabrication environment and operation environment of the semiconductor memory apparatus are variable, a fail is still likely to occur during a read operation based the fixed time tRCD, and an unnecessary operation time may be required.